High speed serial data link systems 100 are composed of a transmitter (Tx) 105, a channel 110, and a receiver (Rx) 115, as shown in FIG. 1. Transmitter 105 sends data signals to receiver 115 over channel 110. As is known in the art, the channel 110 may comprise any physical transmission medium, including copper wire, coaxial cable, optical fiber, or (in the case of wireless transmission) the air. Channel 110 may also comprise multiple mediums.
As high speed serial standards move beyond 6 Gb/s, equalization techniques start being widely deployed, to correct for signal degradation caused by effects in the channel such as channel loss, reflection, cross talk, and noise. In particular, pre-emphasis or de-emphasis techniques may be used in the transmitter 105, while the receiver 115 may use linear equalization techniques such as Continuous Time Linear Equalizers (CTLE) and Feed Forward Equalizers (FFE). Another well-known technique for removing signal degradations, especially those caused by Inter-Symbol interference (ISI) due to channel insertion loss and reflections, or noise from crosstalk and other sources, is the non-linear, decision feedback equalizer (DFE).
Often, each serial data standard requires a specific type of equalization. The USB 3.1 Gen 2 standard, for example, specifies a compliance channel that has insertion loss of 13 dB at the fundamental frequency (5 GHz). To maintain system performance, the USB 3.1 Gen 2 standard specifies that the receiver has a CTLE and a one-tap DFE, as shown in FIG. 2. The CTLE 200 counteracts attenuation caused by the channel, while the DFE 205 attempts to further reduce inter-symbol interference (ISI) in the received data. Receivers that conform to the standard typically have hardware equalization circuits. In contrast, general-purpose measurement devices such as oscilloscopes typically perform equalization in software, since the device may need to use different equalization depending on what standard a received data signal conforms to.
In addition, the data signals sent from the transmitter often include an bedded clock signal that must be recovered by the receiver. Spread-spectrum clocking (SSC) is commonly used in high frequency signals to reduce electromagnetic emissions at the clock frequency. The frequency spectrum for a clock signal that does not have SSC will consist primarily of a single frequency. But when SSC is used, the clock's spectrum will be spread across multiple frequencies. This reduces the magnitude at each individual frequency. But, the wider spectrum of the SSC makes it more sensitive to channel loss. Channel loss typically affects frequencies at the higher end of the data signal's spectrum more than lower frequencies. This spectrum distortion may introduce ISI, making the clock signal with SSC harder to recover. Other signal integrity issues such as cross coupling and other noise, insertion loss, or reflections, may also cause issues.
In addition, SSC introduces low-frequency jitter into the clock signal, which must be removed by the clock recovery in the receiver. Some devices use dedicated clock-recovery circuitry in hardware to remove this jitter, as shown in FIG. 3. When the data signal includes clock data, the received signal 300 may be sent through a clock recovery circuit 305. In one implementation, the clock recovery circuit 305 may comprise a phase-locked loop (PLL). PLL implementations are typically required when the data signal has SSC, because the PLL is able to track out large low-frequency jitter introduced by SSC.
For example, the “Golden PLL” method uses a hardware phase locked loop (PLL) to track out low frequency jitter in the clock signal. FIG. 4 shows an ideal PLL specification. The grey line represents the PLL's ability to track jitter in the recovered clock, where a higher value represents better jitter tracking. The black line represents jitter error. As shown in FIG. 4, the Golden PLL approach will have minimal error for data signals with low-frequency jitter which is the type of jitter introduced by SSC.
In some cases, equalization techniques such as the CTLE and DFE discussed above may be used to track out ISI from data signals with SSC. Software-based clock recovery techniques are preferable for a number of reasons. First, as discussed above, general-purpose devices must often receive a umber of different data signals, each of which may require a different equalization technique. It is generally not practical to include specific clock-recovery or equalization hardware for every type of data signal that the device may receive. Thus, software-based clock recovery allows greater flexibility. Secondly, it is often less expensive to perform clock recovery in software, since it eliminates the need for expensive clock recovery circuitry. Third, software-based clock recovery techniques may perform better than hardware-based clock recovery circuits. For example, hardware clock recovery approaches are often subject to limitations such as temperature-based effects that software approaches do not have. In addition, hardware clock recovery circuits often have their own bandwidth limitations. For example, current hardware-based clock recovery circuits in real-time and sampling oscilloscopes are not capable of recovering clock data from a 60 Gb/s signal. In contrast, software-based clock recovery techniques can be used to recover clock data front these high-speed signals.
Fourth, it can be useful to perform clock recovery and equalization separately. In hardware, however, these processes are often performed by the same circuitry. Performing the clock recovery in software may provide greater flexibility, since the same clock recovery technique can be used with any number of equalization techniques. In some cases, it might also be useful to view the un-equalized clock for analysis or simulation purposes.
Unfortunately, some ex sting software clock recovery techniques may perform poorly for data signals that have high ISI, which for example, can be caused by channel loss or reflections. One software technique, based on edge crossing times, is known as the “Golden Software PLL.” As described in U.S. Pat. No. 6,812,688, the Golden Software PLL approach uses edge crossing times in the data signal to recover the clock signal. This technique does not work well, however, when some of the edge crossings are missing. This may occur when there is high inter-symbol reference, one cause of which is when the data signal has been through a high-loss channel.
FIG. 5 shows an exemplary SSC implementation in which the clock rate is varied between abase unit interval 500 and a greater unit interval 505. For example, between 10 GHz and 9.95 GHz. In this example, SSC introduces roughly 30 kHz of jitter into the data signal. When the data signal has high ISI, like the signal shown in FIG. 6, some of the edge crossings will be missing in the received signal. Points 600, 605, and 610 each represent a section of the received signal that has one or more missing edge crossings. These missing edge crossings will introduce errors when the edge crossing based Golden Software PLL is used, since the approach relies on edge crossing times for clock recovery.
Another existing software-based clock recovery technique known as the spectral line approach uses the following steps to recover a clock signal: (1) acquire a data signal, (2) find its derivative, (3) compute the square or absolute value of the derivative, (4) apply a bandpass filter that is defined according to the ideal PLL specification, and (5) find the edge crossing time of the filtered result. The edge crossing times represent the recovered clock signal. The spectral line approach works well on data signals that have SSC if the data signal has low ISI, but does not work well for data signals that have SSC and high ISI. For example, FIG. 7 represents a data signals obtained after step 4 of the spectral line approach. As depicted in FIG. 7, the “Clock” spectrum 700 is not symmetric around its center frequency, due to effects such as channel loss. As is known in the art, channel loss typically affects a signal's higher frequencies more than its lower frequencies. For example, in spectrum 700, the frequencies close to 9.97 GHz are more attenuated than frequencies closer to 9.96 GHz. In comparison, the spectrum for a bandpass filter based on the ideal PLL specification is symmetric around its center frequency, as shown by spectrum 705. When the distortion of spectrum 700 is severe enough, some edge crossings may be missing during step 5 of the spectral line approach. This may introduce errors into the recovered clock.
These channel loss effects are more problematic for signals with SSC, because SSC widens the clock's spectrum. Signals that have a single clock frequency are not affected as much, because the clock's spectrum is narrow. This makes clock recovery difficult when using the spectral line approach for data signals with SSC that have signal integrity issues such as ISI, cross coupling and other noise, insertion loss, or reflections, all of which may be caused by a lossy channel and environment.
FIG. 8 represents an eye diagram and jitter plot for a clock that was recovered by the spectral line approach. In this example, the received data signal uses the SSC implementation shown in FIG. 6, and has high ISI. As shown by the jitter plot 805, the spectral line approach fails to track out the large low jitter introduced by SSC. This is also reflected by the small eye openings in the eye diagram 800. As shown in plot 805, the jitter in the recovered clock has a period of roughly 33 μs, latch is the same as the SSC period shown in FIG. 5.
Thus, there is a need for improved techniques to recover a stable clock from data signals that have SSC and signal integrity issues such as ISI, cross coupling and other noise, insertion loss, or reflections.